Semiconductor device and system using the same

ABSTRACT

There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set to an OFF state.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of application Ser. No.13/909,293, filed Jun. 4, 2013 which the disclosure of Japanese PatentApplication No. 2012-136591 filed on Jun. 18, 2012 including thespecification, drawings and abstract is incorporated herein by referencein its entirety.

BACKGROUND

The present invention relates to a semiconductor device and technologywhich is applicable to a power semiconductor device and a system usingthe same, for example.

In the large social movement of global environmental conservation, theimportance of the electronics business which reduces an environmentalburden is increasing. Especially, a power semiconductor device (alsocalled a power device hereinafter) is employed in an inverter device ofa railway vehicle, a hybrid vehicle, and an electric vehicle, in aninverter device of an air-conditioner, and in a power supply system ofconsumer devices such as a personal computer. The performanceimprovement of a power device contributes greatly to the powerefficiency improvement of an infrastructure system or a consumer device.The power efficiency improvement means that energy resources necessaryfor operation of a system can be reduced; in other words, it means thereduction of a carbon dioxide emission, that is, the mitigation of theenvironmental burden. Accordingly, research and development aiming atthe performance improvement of the power device are carried out activelyin various companies.

A power device is often formed by employing silicon as a material, as isthe case with an ordinary semiconductor integrated circuit (also calleda device hereinafter). In a power conversion device (such as an inverterdevice) which uses a power device employing silicon (also called Sihereinafter) as a material, in order to reduce the energy loss generatedin the inverter device, active development is performed for optimizingthe element structure of a diode and a switching element and the profileof impurity concentration, thereby realizing a low on-resistance and ahigh current density. Moreover, as a material for power devices, a greatattention has been directed in recent years toward a compoundsemiconductor such as silicon carbide (SiC) and gallium nitride (GaN)which are materials with a larger band gap than silicon (also called awide band gap material hereinafter). The compound semiconductor has alarge band gap and exhibits a destruction withstand voltage about 10times higher than that of silicon. Accordingly, a compoundsemiconductor-based semiconductor device can make its film thicknessthinner than a Si device and can reduce greatly the value of conductionresistance (Ron) of a switching element. Consequently, it is possible toreduce the so-called conduction loss (Ron×i×i), expressed by the productof resistance (Ron) and conduction current (i), contributing to thepower efficiency improvement greatly. Paying attention to such afeature, development work of a diode and a switching element whichutilize the compound semiconductor as a material is being activelyconducted domestically and internationally.

When focusing on a switching device, commercialization of product ispromoted quickly for a junction FET (called JFET hereinafter) as acompound semiconductor which employs SiC as the material. A JFET doesnot require an oxide film as compared with a MOSFET; therefore, thereare few issues of the defect in the interface between the oxide film andthe SiC and of the accompanying degradation of the elementcharacteristic. Moreover, in a JFET, it is possible to control ON andOFF of the JFET by controlling the spread of a depletion layer formed ina PN junction; therefore, it is also easy to manufacture a normally-offelement and a normally-on element separately. In this way, when comparedwith the MOSFET, the JFET has features that it is excellent in the longterm reliability and is easy to manufacture as an element.

However, a normally-off JFET has the following issues. The gate regionand source region of the JFET are semiconductor regions respectivelyhaving P-type conduction and N-type conduction, and have the so-calledPN junction diode structure. Therefore, when the voltage between a gateand a source reaches about 3V, a parasitic diode between the gate andthe source turns into an ON state. As a result, large current may flowbetween the gate and the source and the JFET may generate heatexcessively, leading to breakdown. Accordingly, when the JFET isutilized as a normally-off switching element, it is desirable to utilizethe JFET by limiting the voltage between the gate and the source to alow voltage of about 2.5V, and keeping the JFET in the state where theparasitic diode is not activated into an ON state or in the state wherethe diode current which flows between the gate and the source issufficiently small.

In an ordinary MOSFET made from silicon, a normally-off MOSFET is setinto an ON state, by the application of a gate voltage from 0V to about15V or 20V. Accordingly, in order to utilize a normally-off JFET insteadof a normally-off MOSFET, it is necessary to add to the existing gatedriving circuit of a MOSFET, a step-down circuit (for example, a DC-DCconverter) or a level conversion circuit, etc. which converts the gatevoltage of about 15V or 20V into a voltage of about 2.5V. A designchange and addition of components for that purpose will raise the costof the whole system. In this way, although a JFET has features of beingexcellent in long term reliability and being easy to manufacture, thedrive voltage of a gate is greatly different from that of a generalMOSFET; therefore, there arises an issue that a large design change of adrive circuit becomes necessary, raising the cost of the whole system.

One of the methods of solving the present issue is a cascode connectionmethod disclosed by Patent Literature 1. In the connection method, anormally-on JFET element and a MOSFET of a low withstand voltage arecoupled in series. When coupled in this way, a drive circuit whichdrives a gate will drive the MOSFET; accordingly, it is not necessary tochange the drive circuit. Furthermore, since it is series coupling, thewithstand voltage between a drain and a source as both ends of theseries coupling is determined by the characteristics of the JFET. Evenwhen coupled in series, the on-resistance as a cascode element comprisedof the series coupling of the JFET and the MOSFET is also suppressedcomparatively small, because it is the series coupling of the lowon-resistance of the JFET and the low on-resistance of the MOSFET of alow withstand voltage. In this way, the cascode connection method doesnot require the additional circuit (for example, the step-down circuitor the level conversion circuit described above) which is required whenutilizing a normally-off JFET; accordingly it may be able to provide aneasy-to-use switching element.

Patent Literature 2 discloses that in the cascode connection method, thegates of a JFET and a MOSFET are respectively driven by a drive circuit.In this method, an ON state voltage is applied to the MOSFET at the timeof operation, and the MOSFET is set always in an ON state, as describedin Rows 61 to 66 of Column 1 and Rows 30 to 40 of Column 4 of PatentLiterature 2. In making it operate as a switching element of the cascodeconnection, 0V or a negative potential is applied to the gate of theJFET, thereby making it perform an ON and OFF operation. By such acontrol, it is possible to utilize the feature of the low on-resistancewhich the normally-on JFET has, and it is possible to reduce theconduction loss.

(Patent Literature 1) U.S. Pat. No. 4,663,547

(Patent Literature 2) U.S. Pat. No. 7,777,553

(Non Patent Literature 1) 2SK3069 Datasheet, dated on Sep. 7, 2005

SUMMARY

The examination performed by the present inventors on Patent Literature1 and Patent Literature 2 has revealed that there exists the followingnew issue.

(1) Examination on Patent Literature 1

When examining a circuit disclosed by Patent Literature 1, the circuithas been prepared based on Patent Literature 1 for the purpose ofexamination. The circuit prepared for the purpose of examination isillustrated in FIG. 11. As illustrated in a diagram (A) of FIG. 11, aSiCJFET 113 and a Si-type MOSFET 114 are coupled in cascode to configurea switching element SW1. The switching element SW1 is provided with adrain terminal D, a source terminal S, and a gate terminal G. A gate Gjof the SiCJFET 113 is coupled to a ground potential point of thecircuit, via the source terminal S. An input signal IN0 is supplied tothe gate Gm of the Si-type MOSFET 114 via a drive circuit 112 and thegate terminal G. That is, according to the input signal IN0, a highlevel (a positive potential VDD) or a low level (a ground potentialVSSM) is supplied to the gate Gm of the Si-type MOSFET 114 from the gatedriving circuit (also called a driver circuit hereinafter) 112. In thefigure, a coil depicted by a dashed line indicates a parasiticinductance L1, an arrow directed to a source from a drain of the SiCJFET113 indicates leakage current IDSj, and an arrow directed from a drainto a source of the Si-type MOSFET 114 indicates leakage current IDSm. Asymbol 110 and a symbol 111 depicted by dashed lines indicatesemiconductor chips in which the SiCJFET 113 and the Si-type MOSFET 114are formed, respectively.

Waveforms (B)-(D) of FIG. 11 illustrate operating waveforms of thecircuit illustrated in the diagram (A) of FIG. 11. Next, a new issue isdescribed, with reference to the operating waveforms (B)-(D) of FIG. 11.When the potential of the signal supplied to the gate Gm of the Si-typeMOSFET 114 changes from a high level (a positive potential VDD) to a lowlevel (a ground potential VSSM), as illustrated in the waveform (C) ofFIG. 11, the Si-type MOSFET 114 changes from an ON state to an OFFstate. The SiCJFET 113 is a normally-on transistor of which the gate Gjis supplied with the ground potential (0V) as illustrated in thewaveform (B) of FIG. 11. Therefore, in response to the Si-type MOSFET114 changing to an OFF state, the potential at the drain Sj of theSi-type MOSFET 114 rises, for example to about 5V, as illustrated in thewaveform (D) of FIG. 11. When the potential of the drain Sj rises, thepotential of the gate Gj of the SiCJFET 113 turns into a negativepotential (for example, −5V) relative to the source of the SiCJFET 113,accordingly, the SiCJFET 113 changes to an OFF state. When the Si-typeMOSFET 114 is in an ON state, the potential V_(DSM (ON)) of the drain Sjis set to 0.5V. In this way, the switching element SW1 comprised of thecascode connection is on/off controlled. When the SiCJFET 113 and theSi-type MOSFET 114 are comprised of separate chips (the semiconductorchip 110 and the semiconductor chip 111) as illustrated in FIG. 11, theyare coupled with a bonding wire, for example. Therefore, the parasiticinductance L1 as depicted by the dashed line in FIG. 11 will be formed.The semiconductor chip 110, the semiconductor chip 111, and theparasitic inductance L1 are not illustrated in the drawing of PatentLiterature 1. Because of the existence of the present parasiticinductance L1, a noise of about 20V is transitionally generated in thedrain Sj due to the change of the drain current when the Si-type MOSFET114 changes to an OFF state. Therefore, it is necessary to select atransistor with a sufficiently high withstand voltage (for example, thewithstand voltage BV_(DSS) of 30V) as the Si-type MOSFET 114. Althoughthe Si-type MOSFET 114 and the SiCJFET 113 are both set in an OFF state,leakage currents IDSm and IDSj flow through the Si-type MOSFET 114 andthe SiCJFET 113, respectively, even in the OFF state. When the leakagecurrent IDSj which flows between the drain and the source of the SiCJFET113 and the leakage current IDSm which flows between the drain and thesource of the Si-type MOSFET 114 are balanced, the potential in thedrain Sj of the Si-type MOSFET is maintained at about 5V. However, whenthe OFF-state leakage current IDSj of the SiCJFET 113 is larger than theOFF-state leakage current IDSm of the Si-type MOSFET 114, charges whichflow into the Si-type MOSFET 114 cause the potential of the drain Sj torise continuously, as illustrated in the waveform (D) of FIG. 11. Whenthe potential of the drain Sj of the Si-type MOSFET 114 rises, thepotential of the gate of the SiCJFET 113 becomes more negative relativeto that of the source. Therefore, the leakage current IDSj becomessmall. However, even in this period, the potential of the drain Sj ofthe Si-type MOSFET 114 continues to rise. Therefore, there is apossibility that the withstand voltage BV_(DSS) (for example, 30V) ofthe Si-type MOSFET 114 may be exceeded. When the potential of the drainSj of the Si-type MOSFET 114 exceeds the withstand voltage BV_(DSS), theSi-type MOSFET 114 may start an avalanche operation and large currentmay flow through it. As a result, there is a possibility that the lossin the switching element comprised of the cascade connection mayincrease. It is also considerable to employ a Si-type MOSFET of a highwithstand voltage to configure the cascode connection. However, to makethe withstand voltage high generally means to make the drift layer inthe element thick, leading to the increase of the on-resistance of theSi-type MOSFET 114. Consequently, the on-resistance of the switchingelement may increase.

(2) Examination on Patent Literature 2

When a so-called inverter circuit is comprised of two switching elementsdisclosed by Patent Literature 2 for example, coupling them in seriesbetween power sources and taking out a signal from a coupling node,there arises a possibility that a JFET in the switching element coupledto the low potential side may malfunction (erroneous conduction) and alarge short-circuit current may flow. This phenomenon is explained withreference to FIG. 12. A diagram (A) of FIG. 12 illustrates a circuitwhich has been prepared by the present inventors in order to examine thecontents disclosed by Patent Literature 2. Waveforms (B)-(F) of FIG. 12illustrate operating waveforms of the circuit illustrated in the diagram(A) of FIG. 12.

As illustrated in the diagram (A) of FIG. 12, a switching element SW2comprises a drain terminal D, a source terminal S, gate terminals G0 andG1, a normally-on SiCJFET 123, and a Si-type MOSFET 124 which is coupledin cascade to the normally-on SiCJFET 123. A gate driving circuit 122drives the SiCJFET 123 via the gate terminal G1, in response to an inputsignal IN1. A gate driving circuit 125 drives the Si-type MOSFET 124 viathe gate terminal G0, in response to an input signal IN0. The gatedriving circuit 122 supplies a ground potential VSSJ of the circuit or anegative potential VKK to a gate Gj of the SiCJFET 123 according to theinput signal IN1 as illustrated in the waveform (C) of FIG. 12. On theother hand, the gate driving circuit 125 always supplies a high level (apositive potential VDD) to a gate Gm of the Si-type MOSFET 124 asillustrated in the waveform (D) of FIG. 12.

The switching element SW2 (also called a lower-arm switching elementhereinafter) is coupled in series with a switching element (not shown,also called an upper-arm switching element hereinafter) of the sameconfiguration as the switching element SW2, thereby composing theso-called inverter circuit. That is, the lower-arm switching element andthe upper-arm switching element are coupled in series between thepredetermined potentials. The switching element SW2 indicates theswitching element coupled to the low potential side. Therefore, thedrain terminal D of the lower-arm switching element is coupled to thesource terminal of the upper-arm switching element, and the sourceterminal S of the lower-arm switching element is coupled to a lowpotential point (for example, the ground potential point of thecircuit). In this inverter circuit, an output signal is taken out fromthe node of the upper-arm switching element and the lower-arm switchingelement, by activating exclusively the upper-arm switching element andthe lower-arm switching element into an ON state.

Next, the following describes the case where the lower-arm switchingelement is set in an OFF state and the upper-arm switching element isset in an ON state, according to the input signals IN0 and IN1. Theoperating waveforms of the lower-arm switching element in the presentstate are illustrated in the waveforms (B)-(F) of FIG. 12.

The lower-arm switching element is set in an OFF state. Accordingly, asindicated in the waveform (B) of FIG. 12, a voltage VD between thesource and the drain of the switching element SW2 rises near to thepower supply voltage VCC (for example, 300V). At this time, assumingthat Cgs (not shown) is a parasitic capacitance between the gate and thesource of the SiCJFET 123 and Cgd (not shown) is a parasitic capacitancebetween the gate and the drain, and if a ratio Cgd/(Cgs+Cgd) iscomparatively large, the potential at the gate Gj of the SiCJFET 123rises like a potential VGj by the effect of capacity coupling asillustrated in the waveform (C) of FIG. 12.

The parasitic capacitance of SiCJFET is decided by the depletion layerwidth and the area produced between regions. For example, with referenceto FIGS. 9A and 9B which are to be employed in describing the structureof the SiCJFET according to an embodiment, the narrowest depletion layerwidth is at the region between a gate and a source. This is because theimpurity concentration of a P-type gate region and an N-type sourceregion is comparatively intense compared with other semiconductorregions, and hence the depletion layer width becomes narrow.Consequently, the value of the parasitic capacitance Cgs between thegate and the source becomes large. On the other hand, the opposing areaof a region forming a gate (gate electrode p+gate) and a drift layerDRIFTj is large and impurity concentration is low; however, theparasitic capacitance Cgd between the gate and the drain has a largevalue next to the parasitic capacitance Cgs. As for the parasiticcapacitance Cds between the drain and the source, the entire drift layersandwiched by the gate electrodes p+gate becomes a depletion layer andthe depletion layer width becomes very broad; as a result, the parasiticcapacitance Cds between the drain and the source tends to become smallcompared with the other parasitic capacitance. Accordingly, as describedabove, the capacity ratio Cgd/(Cgs+Cgd) of the parasitic capacitance inthe SiCJFET becomes large compared with that of the general Si-typeMOSFET. The following describes the parasitic capacitance of the Si-typeMOSFET with reference to FIG. 10, which is to be employed in describingthe structure of the Si-type MOSFET according to the embodiment as well.With reference to FIG. 10, the parasitic capacitance Cgs is given by theseries coupling of a capacity Cox due to the oxide film Tox under a gateelectrode GPm and the depletion layer capacitance Cdep; therefore, theparasitic capacitance Cgd between the gate and the drain becomesconsiderably smaller than the parasitic capacitance Cgs between the gateand the source. As a result, the value of the capacity ratioCgd/(Cgs+Cgd) becomes smaller than that of the JFET. Therefore, theSi-type MOSFET is more resistant to generation of erroneous conduction.Although it will be described later, in FIG. 10, a symbol SPm refers toa source electrode and a symbol DRAINm refers to a drain electrode. Thecapacitance characteristics of the Si-type MOSFET is described in NonPatent Literature 1, for example. In Non Patent Literature 1, the inputcapacitance (symbol Ciss) indicates the sum of the parasitic capacitanceCgs and the parasitic capacitance Cgd, the output capacitance (symbolCoss) indicates the sum of the parasitic capacitance Cgd and theparasitic capacitance Cds, and a backward feed capacitance (symbol Crss)indicates the parasitic capacitance Cgd. Therefore, when Non PatentLiterature 1 is referred to, the capacity value of the parasiticcapacitance Cgs is given by the capacity value of the symbol Ciss minusthe capacity value of the symbol Crss, the capacity value of theparasitic capacitance Cgd is given by the capacity value of the symbolCrss, and the capacity value of the parasitic capacitance Cds is givenby the capacity value of the symbol Coss minus the capacity value of thesymbol Crss. A symbol ID illustrated in the waveform (F) of FIG. 12indicates the current between the drain and the source.

In addition to the relation of the capacity ratio described above, thenormally-on SiCJFET has a threshold voltage as low as about −3V becauseof the element characteristic; therefore, the potential at the gate Gjmay rise as illustrated in the waveform (C) of FIG. 12 (the potentialVGj) and erroneously conduct the SiCJFET, and short-circuit current IDPmay flow transitionally between the drain terminal D and the sourceterminal S, as illustrated in the waveform (F) of FIG. 12. It has beenclarified that, in Patent Literature 2, when the switching element isused, the Si-type MOSFET is always held in an ON state in this way,accordingly, the short-circuit current IDP flows to the source terminalS of the switching element and causes a large loss. If the negativepotential VKK (the potential applied to the gate Gj) at the time ofstandby of the SiCJFET is lowered, it may be possible to solve the issueof the short-circuit current. However, the potential difference betweenthe gate and the drain of the SiCJFET increases in this case. Therefore,when a surge potential which exceeds the withstand voltage of theSiCJFET element at the time of switching is generated at the drain nodeof the lower-arm SiCJFET, it is plausible that the SiCJFET elementitself is destroyed. In the diagram (A) of FIG. 12, a symbol 120 and asymbol 121 depicted by dashed lines indicate semiconductor chips inwhich the SiCJFET 123 and the Si-type MOSFET 124 are formed,respectively. When the switching element SW2 is comprised of thesemiconductor chip 120 and the semiconductor chip 121 as illustrated inFIG. 12, they are coupled by a bonding wire as is the case with FIG. 11.Therefore, the parasitic inductance L2 as depicted by the dashed line inFIG. 12 will be formed. The semiconductor chip 120, the semiconductorchip 124, and the parasitic inductance L2 are not illustrated in thedrawing of Patent Literature 2.

The other issues and new features of the present invention will becomeclear from the description of the present specification and theaccompanying drawings.

A semiconductor device according to one embodiment comprises anormally-off silicon transistor and a normally-on compound transistor,which are mutually coupled in cascode. The silicon transistor and thecompound transistor are driven by one input signal, so as to have aperiod in which both transistors are set in an OFF state.

According to the one embodiment, it becomes possible to reduce thepossibility that the semiconductor device is destroyed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing illustrating a circuit diagram of a semiconductordevice according to an embodiment;

FIGS. 2A, 2B and 2C are drawings illustrating operating waveforms of thesemiconductor device according to the embodiment;

FIG. 3 is a drawing illustrating a block diagram of a system accordingto the embodiment;

FIGS. 4A, 4B, 4C, 4D and 4E are drawings illustrating operatingwaveforms of the system according to the embodiment;

FIG. 5 is a drawing illustrating a block diagram of a control circuitand a drive circuit employed in the system according to the embodiment;

FIG. 6 is a drawing illustrating a block diagram of a delay circuitemployed in the system according to the embodiment;

FIG. 7A and FIG. 7B are drawings illustrating plan views of thesemiconductor device according to the embodiment;

FIG. 8A and FIG. 8B are drawings illustrating the structure of a SiCJFETaccording to the embodiment;

FIG. 9A and FIG. 9B are drawings illustrating sectional views of thestructure of the SiCJFET according to the embodiment;

FIG. 10 is a drawing illustrating a sectional view of the structure of aMOSFET according to the embodiment;

FIGS. 11A, 11B, 11C and 11D are drawings illustrating an examinationperformed by the present inventors;

FIGS. 12A, 12B, 12C, 12D, 12E and 12F are drawings illustrating anexamination performed by the present inventors; and

FIG. 13 is a drawing illustrating a block diagram of the systemaccording to the embodiment.

DETAILED DESCRIPTION

In the following description, the same reference symbol is attached to aportion which has the identical function, and the detailed explanationthereof is omitted. In the case where the description is omitted, it isadvised to refer to the description of the corresponding portion towhich the same symbol is attached.

Here, the description method in the present specification is explained.A JFET and a MOSFET are transistors which have a gate, a source, and adrain. A transistor in which current flows through a path between asource and a drain (a source-to-drain path) of the transistor when thegate and the source are substantially set at the same potential iscalled a normally-on transistor in the present specification. Atransistor in which current does not flow substantially through thesource-to-drain path when the gate and the source are substantially setat the same potential is called a normally-off transistor in the presentspecification. It can be also interpreted such that a normally-ontransistor is a depletion-type transistor and a normally-off transistoris an enhancement-type transistor. In order to distinguish a transistormade from silicon and a transistor made from compound semiconductor, inthe present specification, a transistor which employs silicon is calleda Si-type MOSFET, a Si-type JFET, or a silicon transistor. Similarly, atransistor made from the compound semiconductor is expressed byappending a material name before MOSFET and JFET. For example, when SiCis employed as a material, it is described as a SiCJFET. When materialof the compound semiconductor is not specified in particular, it isdescribed as a compound transistor and a compound JFET.

An “inverter” is roughly classified into the following three meanings.In the present specification, the term is properly used as follows forconvenience, according to the three meanings. (1) An inverter device: apower supply circuit which generates ac power electrically from directcurrent power or a power conversion device provided with the powersupply circuit. (2) An inverter circuit: a circuit which configuresapart of the power supply circuit of (1) described above, and in whichtwo switching elements are coupled in series between power sources and asignal is taken out from the node. (3) An inverter: a logical NOT gateas a kind of logic circuit.

Outline of Embodiment

First, the outline of the embodiment is described with reference toFIGS. 1 and 2 which will be described in detail later. FIG. 1illustrates a circuit diagram of a semiconductor device, and FIG. 2illustrates operating waveforms of the circuit illustrated in FIG. 1.

As illustrated in FIG. 1, the semiconductor device SW includes twosemiconductor chips 1 and 2 surrounded with a dashed line, respectively.A normally-on SiCJFET (compound transistor) 3 is formed in thesemiconductor chip 1, and a normally-off Si-type MOSFET (silicontransistor) 4 is formed in the semiconductor chip 2. The semiconductordevice SW is provided with a terminal S and a terminal D in a pair, andthe SiCJFET 3 and the Si-type MOSFET 4 are coupled in series between theterminal D and the terminal S (coupled in cascode). That is, a source ofthe SiCJFET 3 is coupled to a drain of the Si-type MOSFET 4.Accordingly, a source-to-drain path of the SiCJFET 3 is coupled betweenthe terminal S and the terminal D via a source-to-drain path of theSi-type MOSFET 4. In FIG. 1, a drive circuit GD is a circuit for drivingthe semiconductor device SW, and includes gate driving circuits 5 and 6.Input signals IN1 and IN0 are supplied to the gate driving circuits 5and 6, respectively, and the SiCJFET 3 and the Si-type MOSFET 4 aredriven by signals supplied from the gate driving circuits 5 and 6. Aswill be understood from the following description, the input signal IN1and the input signal IN0 are correlating with each other and they aregenerated on the basis of one input signal IN. According to the inputsignal IN, the SiCJFET 3 and the Si-type MOSFET 4 are turned on and off;thereby the semiconductor device SW operates as a switching circuit.That is, one input signal IN is an input signal which controls ON andOFF of the switching circuit. In FIG. 1, a coil depicted with a dashedline indicates a parasitic inductance Lj of a wiring which couples theSiCJFET 3 with the Si-type MOSFET 4. Hereinafter, the semiconductordevice SW is also called a switching circuit SW.

FIG. 2 illustrates the operating waveforms of the semiconductor deviceSW. A waveform (A) of FIG. 2 illustrates the waveform of a signalsupplied to the gate Gj of the SiCJFET 3, and a waveform (B) illustratesthe waveform of a signal supplied to the gate Gm of the Si-type MOSFET4. The high level of the signal supplied to the gate Gj of the SiCJFET 3is a ground potential and the low level is a negative potential. On theother hand, the high level of the signal supplied to the gate Gm of theSi-type MOSFET 4 is a positive potential and the low level is the groundpotential.

When setting the switching circuit SW into an OFF state according to theinput signal IN, the gate driving circuit 5 supplies the negativepotential VKK to the gate Gj, and the gate driving circuit 6 suppliesthe ground potential VSSM to the gate Gm, in response to the inputsignal IN1 and the input signal IN0 which are generated on the basis ofthe input signal IN. Accordingly, the SiCJFET 3 and the Si-type MOSFET 4are set in an OFF state, and it becomes possible to enhance thereduction of a leakage current of the switching circuit SW.

When setting the switching circuit SW into an ON state according to theinput signal IN, it is desirable to set as a high level the signalsupplied to the gate Gm of the Si-type MOSFET 4 earlier than the signalsupplied to the gate Gj of the SiCJFET 3, as illustrated in thewaveforms (A) and (B) of FIG. 2. By this setting, it becomes possible toreduce a surge potential which is generated by the parasitic inductanceLj.

Next, when setting the switching circuit SW into an OFF state accordingto the input signal IN, it is desirable to set as a low level (thenegative potential) the signal supplied to the gate Gj of the SiCJFET 3earlier than the signal supplied to the gate Gm of the Si-type MOSFET 4,as illustrated in the waveforms (A) and (B) of FIG. 2. By this setting,it becomes possible to suppress a surge potential which is generated bythe parasitic inductance Lj.

Accordingly, it is possible to enhance the reduction of the leakagecurrent of the switching circuit (the semiconductor device). It becomesalso possible to reduce a possibility that the switching circuit isdestroyed by the surge potential.

Embodiment 1. A Switching Circuit

As illustrated in FIG. 1, the semiconductor device SW includes twosemiconductor chips 1 and 2. The normally-on SiCJFET 3 is formed in thesemiconductor chip 1, and the normally-off Si-type MOSFET 4 is formed inthe semiconductor chip 2. The SiCJFET 3 and the Si-type MOSFET 4 arecoupled in cascade between the terminal D and the terminal S which areprovided in the semiconductor device SW. That is, the source-to-drainpath of the SiCJFET 3 and the source-to-drain path of the Si-type MOSFET4 are coupled in series between the terminal S and the terminal D. Asignal from the drive circuit GD is supplied to the semiconductor deviceSW. In the drive circuit GD, the gate driving circuits 5 and 6 receivesignals IN1 and IN0 changing according to the input signal IN, andsupply the signals changing according to the input signal IN to theterminals G1 and G0 of the semiconductor device SW. The terminal G1 iscoupled to the gate Gj, and the terminal G0 is coupled to the gate Gm.The SiCJFET 3 and the Si-type MOSFET 4 turn on and off according to thepotential of the input signal IN. That is, the semiconductor device SWoperates as a switching circuit which makes a path between the terminalS and the terminal D conductive or non-conductive according to the inputsignal IN (hereinafter, the semiconductor device SW is also called aswitching circuit SW). In the present embodiment, the terminal S is asource of the switching circuit SW, and the terminal D is a drain of theswitching circuit SW. However, it should be noted that the expression ofa source and a drain changes depending on the direction of the currentsupplied to the switching circuit SW. The source electrode Sj of theSiCJFET 3 is coupled to the drain electrode of the Si-type MOSFET 4;accordingly, the source electrode Sj of the SiCJFET 3 may indicate thedrain electrode of the Si-type MOSFET 4.

FIG. 2 illustrates the driving waveforms of the semiconductor device SWillustrated in FIG. 1. When making the path between the source S and thedrain D of the switching circuit SW non-conductive, the negativepotential VKK (for example, −20V) is applied to the gate Gj of theSiCJFET 3, according to the input signal IN. At this time, the potentialVSSM equal to the ground level (for example, 0V) is applied to the gateGm of the Si-type MOSFET 4 according to the input signal IN.Accordingly, the SiCJFET 3 and the Si-type MOSFET 4 are both set into anOFF state. Next, when making the path between the source S and the drainD of the switching circuit SW conductive, the potential of the gate Gmof the Si-type MOSFET 4 is set to the positive potential VDD (forexample, 15V) from the ground potential VSSM according to the inputsignal IN, and the Si-type MOSFET 4 is set into an ON state. After apredetermined time tdA, the potential of the gate Gj of the SiCJFET 3 isshifted from the negative potential VKK to the potential VSSJ (forexample, 0V) equal to the ground potential according to the input signalIN, and the SiCJFET 3 is set into an ON state. At this point, if theSiCJFET 3 is set to an ON state earlier than the Si-type MOSFET 4, asurge potential may be generated by the parasitic inductance Lj whichexists in the source of the SiCJFET 3, and the drain potential of theSi-type MOSFET 4 may rise higher than the withstand voltage. Therefore,in the present embodiment, the Si-type MOSFET 4 is driven earlier thanthe SiCJFET 3, and the source S of the switching circuit SW and thesource Sj of the SiCJFET 3 is electrically coupled. Accordingly, itbecomes possible to suppress a noise due to a surge. The SiCJFET 3 andthe Si-type MOSFET 4, which are coupled in cascode, are both set in anON state according to the input signal IN, thereby the switching circuitSW is set in an ON state, and the switching circuit SW is set in theconductive state. The potential of the source electrode Sj of theSiCJFET 3 at this time becomes equal to an ON state voltage of theSi-type MOSFET 4, that is, about 0.5V, for example.

Next, the following describes the operation of turning off the switchingcircuit SW according to the input signal IN. First, the potential of thegate Gj of the SiCJFET 3 is shifted from the ground potential VSSJ tothe negative potential VKK. Next, after the desired delay time tdB, thepotential of the gate Gm of the Si-type MOSFET 4 is shifted from thepositive potential VDD to the ground potential VSSM. Accordingly, theSiCJFET 3 and the Si-type MOSFET 4 are both set in an OFF state and thecascade switching element (the semiconductor device or the switchingcircuit) SW is set in an OFF state. In the present embodiment, theSiCJFET 3 is set in an OFF state prior to the Si-type MOSFET 4.Accordingly, it is possible to suppress the generation of a surgepotential at the source electrode Sj of the SiCJFET 3. Consequently,when turning off the switching circuit SW, it is desirable to drive theSiCJFET 3 in advance. By applying the driving as illustrated in FIG. 2,the OFF state voltage at the time of the standby when the SiCJFET 3 isin an OFF state becomes the negative potential VKK (for example, −20V).Therefore, it is possible to reduce the leakage current IDSj which isgenerated in the SiCJFET 3 immediately after the SiCJFET 3 is set intoan OFF state. Consequently, even if the leakage current IDSj of theSiCJFET 3 at this time is larger than the leakage current IDS of theSi-type MOSFET 4 at this time and the potential of the source electrodeSj of the SiCJFET 3 rises as the result, the voltage which is adifference of the risen amount of potential dVSj (for example, 20V) andthe potential of the gate Gj of the SiCJFET 3 (the negative potentialVKK) is applied between the gate and the source of the SiCJFET 3.According to the example, the voltage of “the negative potential VKK−thepotential dVSj=−40V” is applied between the gate and the source of theSiCJFET 3. Accordingly, it becomes possible to fully reduce the leakagecurrent IDSj which is generated in the SiCJFET 3. As a result ofreducing the leakage current IDSj, it is possible to lengthen enough thetime required for the potential in the drain of the Si-type MOSFET 4 torise. Thereby, the potential rise at the drain Sj of the Si-type MOSFET4 is suppressed low, in the cycle of the frequency at which theswitching circuit SW switches (switching frequency). Therefore, it ispossible to prevent the avalanche operation in the Si-type MOSFET asdescribed above. In other words, the rise of the drain potential of theSi-type MOSFET 4 is suppressed; therefore, it is not necessary to designthe withstand voltage of the Si-type MOSFET 4 unduly high. That is,since element structure which has a comparatively low withstand voltagecan be adopted, it becomes possible to reduce the on-resistance of theSi-type MOSFET 4 and to reduce the loss of the switching element(switching circuit). Here, the element structure which has acomparatively low withstand voltage means the structure in which thefilm thickness is reduced or the concentration is increased, in thedrift layer DRIFTm illustrated in FIG. 10, for example.

The configuration for providing the desired delay times tdA and tdB inthe above is not described here, because one example of theconfiguration will be described later with reference to FIGS. 5 and 6.In FIG. 1, the diode coupled between the source and the drain of theSi-type MOSFET 4 indicates a parasitic diode. The same holds true forother figures (for example, FIG. 3).

2. An Inverter Circuit and a System Using the Same

Next, the following describes an example in which the semiconductordevice SW and the drive circuit GD described with reference to FIG. 1are applied to a system. Here, as an example of the application, asystem of a motor driven by a three-phase inverter circuit is described.

FIG. 3 illustrates a block diagram of a system SYS of a three-phaseinverter circuit 3INV which drives a three-phase motor LOAD according toan input signal. Each of switching circuits SWU, SWV, SWW, SWX, SWY, andSWZ has the same configuration as the semiconductor device SWillustrated in FIG. 1. The drive circuit GD provided pertaining to thesemiconductor device SW is illustrated as drive circuits GDU, GDV, GDW,GDX, GDY, and GDZ in FIG. 3. That is, the three-phase inverter circuit3INV has the semiconductor device and the pertaining drive circuit whichare illustrated in FIG. 1 in groups of six. In order to configure aninverter circuit, two semiconductor devices (a first semiconductordevice and a second semiconductor device) each operating as a switchingcircuit are coupled in series between a plus side P and a negative sideN of a DC power supply DPS, and the two semiconductor devices coupled inseries perform a complementary switching operation with each otheraccording to an input signal. The power supply voltage which is apotential difference of the potential VCC of the plus side P and theground potential of the negative side N of the DC power supply DPS is300V, for example. By the complementary switching operation, a drivingsignal is outputted from a node of the two semiconductor devices to themotor as a load device. In the example illustrated in FIG. 3, thesemiconductor device SWU and the semiconductor device SWX are coupled inseries to configure an inverter circuit INV_U, and a signal is outputtedfrom the node to drive a U phase of the three-phase motor LOAD as theload device. Similarly, the semiconductor device SWV and thesemiconductor device SWY are coupled in series to configure an invertercircuit INV_V, and a signal is outputted from the node to drive a Vphase of the three-phase motor LOAD as the load device. Thesemiconductor device SWW and the semiconductor device SWZ are coupled inseries to configure an inverter circuit INV_W, and a signal is outputtedfrom the node to drive a W phase of the three-phase motor LOAD as theload device. In FIG. 3, reflux diodes Diu, Div, Diw, Dix, Diy, and Dizare coupled respectively between a terminal S and a terminal D of thesemiconductor devices SWU, SWV, SWW, SWX, SWY, and SWZ. A capacitor C0is coupled between the plus side P and the negative side N of the DCpower supply DPS.

FIG. 4 illustrates operating waveforms of the three-phase invertercircuit 3INV illustrated in FIG. 3. Since each phase performs the sameoperation, FIG. 4 illustrates only the operating waveform of theinverter circuit INV_U which generates the driving signal to drive the Uphase of the three-phase motor LOAD. In the following description, amongthe two semiconductor devices and two drive circuits which configure aninverter circuit, the semiconductor device SWU coupled to the plus sideP of the DC power supply DPS and the pertaining drive circuit GDU arecalled an upper arm, and the semiconductor device SWX coupled to thenegative side N of the DC power supply DPS and the pertaining drivecircuit GDX are called a lower arm.

With reference to FIG. 4, the following describes the operation of thethree-phase inverter circuit 3INV illustrated in FIG. 3, taking the Uphase as an example. The waveforms (A)-(E) of FIG. 4 are operatingwaveforms of the lower arm. Since it is an inverter circuit, theswitching circuit (the semiconductor device) SWU of the upper arm andthe switching circuit (the semiconductor device) SWX of the lower armoperate complementarily according to an input signal. For example, thecontrol is performed by the input signal such that, when the lower-armswitching circuit SWX is in an OFF state, the upper-arm switchingcircuit SWU shifts to an ON state. FIG. 4 illustrates the state where,up to time t, the lower-arm switching circuit SWX is in an ON state andthe upper-arm switching circuit SWU is in an OFF state. At time t, thelower-arm switching circuit SWX is set to an OFF state, and theupper-arm switching circuit SWU shifts to an ON state. In order that theswitching circuit SWU can shift to an ON state, the potential VD at theterminal D of the lower-arm switching circuit SWX rises to near thepotential VCC of the power supply voltage. Thereby, the potential at thedrain of the SiCJFET (corresponding to the SiCJFET 3 illustrated inFIG. 1) of the switching circuits SWX rises rapidly. As previouslydescribed with reference to FIG. 12, the potential at the gate Gj of theSiCJFET also rises transitionally with the rise of the potential at thedrain of the SiCJFET. As a result, a charge flows in from the drain ofthe SiCJFET, and although it is temporary, the potential of the drain Sjof the Si-type MOSFET (corresponding to the Si-type MOSFET 4 illustratedin FIG. 1) rises. Here, in the circuit illustrated in FIG. 12, theSi-type MOSFET is in an ON state at this time, therefore, theshort-circuit current will flow into the terminal S of the switchingcircuit SWX. However, according to the present embodiment, the potentialat the gate Gm is set to a low level, therefore, the Si-type MOSFET isset to an OFF state at this time. For that reason, the short-circuitcurrent does not flow to the terminal S of the switching circuit SWX, inother words, it is possible to reduce the loss of the switching circuit.The potential at the drain Sj of the Si-type MOSFET rises due to theinflow of a charge, as described above, however, by suitably andtemporarily turning on the switching circuits SWU and SWX one by onewhen the upper-arm switching circuit SWU and the lower-arm switchingcircuit SWX of the U phase are both in an OFF state, the charge storedin the drain of the Si-type MOSFET can be extracted to the terminal S,and the potential at the drain of the Si-type MOSFET can be reduced.

In FIG. 4, the operating waveforms (B)-(D) before time t are the same asthe operating waveforms (A)-(C) illustrated in FIG. 2 described above,therefore, the description thereof is omitted here.

FIG. 5 illustrates a block diagram of a gate-driver control circuitGDCTL and a drive circuit GD for generating the waveforms illustrated inFIGS. 2 and 4. In FIG. 5, the portion illustrated on the right-hand sideof a dashed line is the drive circuit GD, and the portion illustrated onthe left-hand side of the dashed line is the gate-driver control circuitGDCTL. The gate-driver control circuit GDCTL and the drive circuit GDwhich correspond to one inverter circuit are illustrated in the figure.Consequently, when driving the three-phase motor LOAD illustrated inFIG. 3, three groups of the configurations illustrated in FIG. 5 areemployed. Here, an example of driving the U phase of FIG. 3 among threephases is described. That is, FIG. 5 illustrates a gate-driver controlcircuit GDCTL and a drive circuit GD which correspond to the invertercircuit INV_U (the switching circuit SWU and the switching circuit SWX)for driving the U phase illustrated in FIG. 3. The drive circuits GDUand GDX are illustrated also in FIG. 3, and the correspondence betweenFIG. 3 and FIG. 5 should be understood as follows: that is, the gatedriving circuits GD_U0 and GD_U1 included in the drive circuit GD (FIG.5) correspond to the gate driving circuits included in the drive circuitGDU of FIG. 3, and the gate driving circuits GD_X0 and GD_X1 correspondto the gate driving circuits included in the gate driving circuit GDX ofFIG. 3. In FIG. 3, in order to avoid the drawing from becomingcomplicated, the input signals of each gate driving circuit are notshown.

First, the gate-driver control circuit GDCTL is described. Thegate-driver control circuit GDCLT receives input signals for eachsemiconductor device (switching circuit) to control. In FIG. 5, an inputsignal HIN for controlling the switching circuit SWU and an input signalLIN for controlling the switching circuit SWX are supplied to thegate-driver control circuit GDCTL. The gate-driver control circuit GDCTLgenerates input signals IN0 and IN1 according to the input signal HIN(the input signal LIN) and supplies them to the gate driving circuitsGD_U0 and GD_U1 (the gate driving circuits GD_X0 and GD_X1).Accordingly, the switching circuit SWU (the switching circuit SWX) isdriven according to the input signal HIN (the input signal LIN). Whendriving the three-phase inverter circuit 3INV illustrated in FIG. 3,since the upper arm and the lower arm are different in voltage toprocess therein, the voltage supplied to the circuit which processes theinput signal FIN and the voltage supplied to the circuit which processesthe input signal LIN are different, in the gate-driver control circuitGDCTL and the gate driving circuit GD, illustrated in FIG. 5. In FIG. 5,as for the power supply potential to be supplied to blocks and otherswhich do not indicate the power supply potential, it is sufficient toselect the power supply potential depending on the potential of thesignal to be processed in each of the blocks and others.

The input signal FIN supplied to the gate-driver control circuit GDCTLis supplied to a level conversion circuit (V_(DD)/V_(CC) LEVEL SHIFT) 51via a Schmitt trigger circuit SHTRG. By employing the Schmitt triggercircuit SHTRG and a resistor R, it is possible to supply an outputsignal of a stabilized level to a level conversion circuit 51 even whenthe input signal HIN fluctuates. An output signal of the levelconversion circuit 51 is supplied to a pulse generator/delay circuit(PULSE GEN & DELAY) 52, and an output signal of the latter is suppliedto a level shift circuit 53. The level shift circuit 53 is comprised ofa Si-type MOSFET (NM) and a resistor R1. An output signal of the levelshift circuit 53 is supplied to RS latch circuits (RS LATCH) 55-0 and55-1 via an interlock circuit/delay circuit (INTERLOCK & DELAY) 54.Output signals of the RS latch circuits 55-0 and 55-1 are supplied tothe gate driving circuits GD_U0 and GD_U1. The input signal LIN issupplied to a level shift circuit 51 via a Schmitt trigger circuitSHTRG. An output signal of the level shift circuit 51 is supplied to NORgates NOR0 and NOR1 via a delay circuit (DELAY) 56, and output signalsof the NOR gates NOR0 and NOR1 are supplied as the input signals IN0 andIN1 to the gate driving circuits GD_X0 and GD_X1. As is the case withthe input signal HIN, by employing the Schmitt trigger circuit SHTRG andthe resistor R in the input stage, it is possible to supply an outputsignal of a stabilized level to the delay circuit 56.

In FIG. 5, a source voltage drop protection circuit (UV DETECT) 57deactivates the gate driving circuit when the power supply voltagedrops, and prevents the switching element from being destroyed.

The gate driving circuits GD_U0 and GD_U1 drive the upper-arm switchingcircuit SWU by the signals from output terminals HO0 and HO1. In orderto generate a drive voltage for driving, the gate driving circuits GD_U0and GD_U1 are supplied with, as the operation potentials, a positivepotential VB on the high potential side, a ground potential VS of thecircuit, and a negative potential VE on the high potential side. Here,the negative potential VE is generated on the basis of the groundpotential VS for the circuit. In response to the signal IN1 from the RSlatch circuit 55-1 as an input signal, the gate driving circuit GD_U1supplies a driving signal to the gate of the SiCJFET in the switchingcircuit SWU (corresponding to the SiCJFET 3 illustrated in FIG. 1). Onthe other hand, in response to the signal IN0 from the RS latch circuit55-0 as an input signal, the gate driving circuit GD_U0 supplies adriving signal to the gate of the Si-type MOSFET in the switchingcircuit SWU (corresponding to the Si-type MOSFET 4 illustrated in FIG.1).

The gate driving circuits GD_X0 and GD_X1 drive the lower-arm switchingcircuit SWX with signals from the output terminals LO0 and LO1. In orderto generate a drive voltage for driving, the gate driving circuits GD_X0and GD_X1 are supplied with, as the operation potentials, a positivepotential VCC on the low potential side, a ground potential VSS of thecircuit, and a negative potential VEE on the low potential side. Here,the negative potential VEE is generated on the basis of the groundpotential VSS for the circuit. In response to the signal IN1 from theNOR gate NOR1 as an input signal, the gate driving circuit GD_X1supplies a driving signal to the gate of the SiCJFET in the switchingcircuit SWX (corresponding to the SiCJFET 3 illustrated in FIG. 1). Onthe other hand, in response to the signal IN0 from the NOR gate NOR0 asan input signal, the gate driving circuit GD_X0 supplies a drivingsignal to the gate of the Si-type MOSFET in the switching circuit SWX(corresponding to the Si-type MOSFET 4 illustrated in FIG. 1). Althoughnot restricted in particular, the negative potentials VE and VEE aregenerated by a voltage regulator (not shown).

Next, operation of the gate-driver control circuit GDCTL illustrated inFIG. 5 is described. When the input signal LIN is asserted, a high levelpotential of the input signal LIN is converted into a positive potentialVCC which is the high level potential of the gate driving circuits GD_X0and GD_X1, by the level conversion circuit 51. The level-convertedsignal is supplied to the gate driving circuits GD_X0 and GD_X1 as theinput signals IN0 and IN1 via the delay circuit 56 and the NOR gatesNOR0 and NOR1. Thereby, the gate driving circuits GD_X0 and GD_X1 drivethe gates Gj and Gm with the driving signals illustrated in thewaveforms (A) and (B) of FIG. 2 and the waveforms (B) and (C) of FIG. 4,according to one input signal LIN. Similarly, the input signal HIN isconverted in level in the level conversion circuit 51, and convertedinto a timing signal with desired timing by the pulse generator/delaycircuit 52. That is, in response to the input signal HIN, a pulsegenerator included in the pulse generator/delay circuit 52 outputs thetiming signal which specifies the rising and falling of the outputsignal in the upper arm. The timing signal generated by the pulsegenerator/delay circuit 52 is supplied to the interlock circuit/delaycircuit 54 via the level conversion circuit 53, and is supplied to theRS latch circuits 55-0 and 55-1. When unfixed signals other than theregular input signal are inputted, an interlock circuit included in theinterlock circuit/delay circuit 54 controls not to transfer the signalto the latter RS latch circuits 55-0 and 55-1 and not to assert theoutput signal in the upper arm. The signal from the RS latch circuits55-1 and 55-0 are supplied to the gate driving circuits GD_U1 and GD_U0as the input signals IN1 and IN0, and the driving signals illustrated inthe waveforms (A) and (B) of FIG. 2 and the waveforms (B) and (C) ofFIG. 4 are outputted from the gate driving circuit GD_U1 and GD_U0 tothe gates Gj and Gm. However, since the gate driving circuits GD_U1 andGD_U0 correspond to the upper arm, the potential of each of the signalswhich drive the gates Gj and Gm is the potential corresponding to theupper arm. In this way, the driving signals for driving separately theSiCJFET and the Si-type MOSFET which configure the switching circuit SWare generated by the gate-driver control circuit GDCTL and the gatedriving circuit GD, on the basis of one input signal (for example, theinput signal LIN).

FIG. 6 illustrates an example of the delay circuit for generating thedelay time tdA and the delay time tdB described above. Here, theexplanation is made about an example of a delay circuit to be applied tothe delay circuit 56 corresponding to the lower arm illustrated in FIG.5. In FIG. 6, an input signal Input to the delay circuit 56 correspondsto the signal supplied via the level conversion circuit 51 illustratedin FIG. 5. When the input signal Input is asserted to a high level, theNOR gate NOR outputs a low level and it is inputted into the inverter63. The inverter 63 outputs to the NOR gate NOR0 in the latter stage(refer to FIG. 5) a high level which is an inverted signal of the outputsignal of the NOR gate NOR, and asserts the gate of the Si-type MOSFET(corresponding to the Si-type MOSFET 4 illustrated in FIG. 1, and alsocalled the Si-type MOSFET 4 in the present paragraph). After that, asignal which is delayed by the delay time tdA by the delay circuit 61Acomprised of the plural inverters is inputted into the NAND gate NAND.Accordingly, the NAND gate NAND outputs a low level and it is inputtedinto the inverter 62. The inverter 62 outputs to the NOR gate NOR1 ofthe latter stage (refer to FIG. 5) a low-level signal which is aninverted signal of the output signal of the NAND gate NAND, and assertsthe gate of the SiCJFET (corresponding to the SiCJFET 3 illustrated inFIG. 1 and also called the SiCJFET 3 in the present paragraph) after thedelay time tdA. When turning off the switching circuit SW, the delaytime tdB of the delay circuit 61B comprised of plural inverters isutilized. By asserting the input signal to a low level, the SiCJFET 3 isset to an OFF state in advance, the NOR gate NOR outputs a high levelafter the delay time tdB, and the inverted signal propagates to the gateof the Si-type MOSFET 4, setting the Si-type MOSFET 4 into an OFF state.When the delay circuit 56 operating as described above is employed, itis possible to freely control the driving time of the SiCJFET 3 and theSi-type MOSFET 4. It is needless to say that the length of the delaytime can be changed by increasing or decreasing the number of stages ofthe inverters in the delay circuits 61A and 61B. When the gate-drivercontrol circuit GDCTL is configured by employing such a circuit, itbecomes possible to generate the waveforms illustrated in FIGS. 2 and 4and to reduce a loss in the switching circuit.

Each block illustrated in FIGS. 5 and 6 can be realized by combining awell-known logic circuit and a sequential circuit; therefore,description of the circuit configuration of each block is omitted. Whatis necessary is just to enable it to generate the driving signals of thegates Gj and Gm illustrated in FIGS. 1 and 4 on the basis of one inputsignal, therefore, the configuration illustrated in FIGS. 5 and 6 ismerely an example.

The gate-driver control circuit GDCTL and the drive circuit GDillustrated in FIG. 5 may be formed in one semiconductor chip, or may beformed separately in different semiconductor chips. The switchingcircuit SW and the gate-driver control circuit GDCTL may also be formedin the same semiconductor chip. Furthermore, the switching circuit SW,the gate-driver control circuit GDCTL, and the drive circuit GD may beformed in the same semiconductor chip.

As for the negative potentials VE and VEE to be supplied to the upperarm and the lower arm, by providing a regulator in the exterior of thesemiconductor chip, the potential generated by the regulator may besupplied to the drive circuit. Naturally, the negative power regulatormay be built in a semiconductor chip, together with the gate-drivercontrol circuit GDCTL and the drive circuit GD. In this way, it ispossible to realize the drive circuit according to the presentembodiment by adding the minimum necessary circuits, such as the delaycircuit 56, to the configuration of the general-purpose semiconductorintegrated circuit for a drive circuit. Therefore, it is possible toreduce the additional cost for realizing the drive circuit.

The example in which the semiconductor device according to the presentembodiment is applied to the three-phase inverter circuit is illustratedin FIG. 3. However, it is also possible to apply the semiconductordevice according to the present embodiment to a system in which the loaddevice is a coil for example and the load device is driven by oneinverter circuit. In this case, as illustrated in FIG. 13, the systemSYS1 comprises a load device LOAD1, such as a coil, an inverter circuitINV for driving the load device LOAD1, and a control circuit CTL forcontrolling the inverter circuit INV. It should be understood asfollows: that is, the inverter circuit INV has the same configuration asthe inverter circuit INV_U corresponding to the U phase, as describedwith respect to FIG. 3, and the control circuit CTL comprises thegate-driver control circuit GDCTL and the drive circuit GD, as describedwith reference to FIGS. 5 and 6. Here, the switching circuit (the firstsemiconductor device) HSW and the switching circuit (the secondsemiconductor device) LSW have the same configuration as the switchingcircuit (the semiconductor device) SW illustrated in FIG. 1. The drivecircuit HGD comprises the gate driving circuits GD_U1 and GD_U0illustrated in FIG. 5, and the drive circuit LGD comprises the gatedriving circuits GD_X1 and GD_X0 illustrated in FIG. 5. The gate-drivercontrol circuit LCTL corresponds to the lower half of the block diagramof the gate-driver control circuit GDCTL illustrated in FIG. 5, andcomprises the Schmitt trigger circuit SHTG, the resistor R, the levelconversion circuit 51, the delay circuit 56, the source voltage dropprotection circuit 57, and the NOR gates NOR0 and NOR1. The gate-drivercontrol circuit I=corresponds to the upper half of the block diagram ofthe gate-driver control circuit GDCTL illustrated in FIG. 5, andcomprises circuits other than the circuits which are included in thelower half of the block diagram described above. The inverter circuitINV is coupled between the positive potential Vcc and the groundpotential Vss. That is, the silicon transistor and the compoundtransistor in each of the first and the second semiconductor device HSWand LSW in the system SYS1 are driven so as to have a period in whichthe both transistors are in an OFF state.

Furthermore, the upper-arm switching circuits HSW, SWU, SWV, and SWW,which configure the inverter circuit of the systems SYS and SYS1, may bedriven in the same manner as in the switching circuit SW2 illustrated inFIG. 12. That is, the silicon transistor and the compound transistor ofeach of the switching circuits HSW, SWU, SWV, and SWW may not have aperiod in which the both transistors are in an OFF state. What isnecessary is to drive the silicon transistor and the compound transistorof each of the lower-arm switching circuit LSW, SWX, SWY, and SWZ so asto have a period in which the both transistors are in an OFF state.Accordingly the gate-driver control circuit can be simplified ratherthan the gate-driver control circuit GDCTL illustrated in FIG. 5.

3. Structure of the Semiconductor Device

FIGS. 7A and 7B illustrate a semiconductor device in which the Si-typeMOSFET 4 and the SiCJFET 3 illustrated in FIG. 1 are sealed in onepackage. FIG. 7A illustrates a plan view of the semiconductor devicesealed with resin, and FIG. 7B illustrates a plan view of thesemiconductor device of which the resin is removed. As illustrated inFIG. 7A, the semiconductor device 70 is covered with sealing resin 72except for leads of the gate terminals G0 and G1, the drain terminal D,the source terminal S, etc. and a header 71. FIG. 7B illustrates anexample in which among two metal plates PLATE1 and PLATE 2 to be sealedwith the sealing resin 72, a semiconductor chip 2 provided with theSi-type MOSFET 4 is arranged in the metal plate PLATE2 on the right-handside, and a semiconductor chip 1 provided with the SiCJFET 3 is arrangedin the metal plate PLATE1 on the left-hand side. By employing a bondingwire, a gate pad GPm coupled to the gate electrode Gm of the Si-typeMOSFET 4 is coupled to the gate terminal G0 which is a lead (a firstlead) projecting from the sealing resin 72, and a source pad SPm coupledto the source electrode Sm is coupled to the source terminal S which isa lead (a second lead) projecting from the sealing resin 72. The sourcepad SPm and the source terminal S are coupled with plural bonding wires.The drain electrode located in the back of the semiconductor chip 2 iscoupled to the metal plate PLATE2 with a die bonding material. On theother hand, by employing a bonding wire, a gate pad GPj coupled to thegate electrode Gj of the SiCJFET 3 on the left-hand side is coupled tothe gate terminal G1 which is a lead (a third lead) projecting from thesealing resin 72, and a source pad SPj coupled to the source electrodeSj is coupled to the metal plate PLATE2, that is, the drain electrode ofthe Si-type MOSFET 4. The source pad SPj and the metal plate PLATE2 arecoupled by plural bonding wires. The drain electrode located in the backof the semiconductor chip 1 is coupled to the metal plate PLATE1 with adie bonding member. The metal plate PLATE1 and the drain terminal Dwhich is a lead (a fourth lead) projecting from the sealing resin 72 areformed in one body. As illustrated in FIG. 7B, the chip area of thesemiconductor chip 2 is smaller than the chip area of the semiconductorchip 1.

By adopting the arrangement and coupling configuration of thesemiconductor chip as described above, it is possible to shorten thelength of the bonding wire which couples the gate electrodes of theSiCJFET 3 and the Si-type MOSFET 4 and the leads, and the length of thebonding wire which couples the source electrode and the lead. That is,it is possible to reduce the parasitic inductance Lj of the bonding wireand the parasitic resistance (on-resistance component) originating fromthe bonding wire. Therefore, it is possible to reduce a noise at thetime of switching and to prevent a surplus potential from being appliedto the Si-type MOSFET. In other words, it is possible to set thewithstand voltage of the Si-type MOSFET at a low value; therefore, it ispossible to reduce the on-resistance of the entire elements which arecoupled in a cascade switch, leading to a reduced loss. The right-handside metal plate PLATE2, which is an opposed electrode of the bondingwire coupled to the source electrode of the SiCJFET, can take a largeportion of margin where the semiconductor chip provided with the Si-typeMOSFET is not arranged. Therefore, it becomes possible to couple thesource electrode of the SiCJFET with the metal plate PLATE2, by use of aclip bonding-type coupling member with a large contact area (aplate-shaped metal, for example, a Cu frame); accordingly there is alsoan advantage that the contact resistance can be reduced. Since at leasttwo or more number of wires can be bonded, it also becomes possible tofurther reduce the parasitic inductance produced in the intermediatenode (the drain Sj) which is a coupling point of the Si-type MOSFET andthe SiCJFET. Furthermore, since plural chips are arranged in a plane, itis possible to freely design the area of the semiconductor chip in whichthe Si-type MOSFET and/or the SiJFET are formed. Therefore, the designof low on-resistance and the design of on-state current density alsobecome easy, and it becomes possible to realize the semiconductor device(the power semiconductor device) of more various specifications.

FIG. 8A illustrates a plane layout of the semiconductor chip 1 in whichthe SiCJFET 3 is formed. The gate pad GPj and the source pad SPj arearranged on the surface (upper surface) of the semiconductor chip 1, andthe drain electrode DRAINj is arranged on the reverse side (undersurface) of the semiconductor chip 1. That is, the semiconductor chip 1is a so-called vertical-type JFET. The area of the source pad SPj ismade larger than the area of the gate pad GPj. The source pad SPj has anadjoining portion which faces two sides of the gate pad GPj. The end ofa termination region TMj is located between the end of the semiconductorchip 1 and the source pad SPj or the gate pad GPj. The terminationregion TMj is located between an active element region ACTj and the endof the semiconductor chip 1. That is, the termination region TMj islocated in the exterior of the active element region ACTj. The gate padGPj is located in the corner formed by intersecting two sides of thesemiconductor chip 1. The gate pad GPj is located over the terminationregion TMj. The end of the active element region ACTj is located at theinner side of the source pad SPj. It is possible to arrange the positionof the gate pad GPj freely by rotating the semiconductor chip 1;therefore, when implementing the semiconductor chip 1 as illustrated inFIG. 7B, it is possible to arrange it so that the wire length of thewire bonding may be shortened.

FIG. 8B is a sectional view illustrating the cross section of an A-A′section in FIG. 8A. A drift layer DRIFTj is located over a compoundsemiconductor substrate SUBj. A drain electrode DRAINj is located underthe compound semiconductor substrate SUBj. That is, the drain electrodeDRAINj is arranged on the reverse side (under surface) of thesemiconductor chip 1. A gate electrode p+gate is located over the driftlayer DRIFTj in the active element region ACTj, and a source electroden+source is located over the gate electrode p+gate. A semiconductorregion pTMj which forms a termination region TMj is arranged over thedrift layer DRIFTj in the termination region TMj. The source pad SPj islocated over the semiconductor region pTMj and the source electroden+source, through an interlayer insulation film Lay1. Serving as thesource pad SPj is a section which is a part of a conductor layer such asaluminum located over the interlayer insulation film Lay1 and which isnot covered by an oxide film SiO2 as a passivation film over theconductor layer. By arranging the termination region pTMj around theactive element region ACTj, it is possible to secure the active elementregion sufficiently in the semiconductor chip; accordingly, it becomespossible to increase the on-state current, that is, to reduce theon-resistance.

FIG. 9A and FIG. 9B illustrate principal part sectional views of theactive element region ACTj of the SiCJFET 3. FIG. 9A illustrates a crosssection of the vertical-type SiCJFET which has a trench structure, thatis, FIG. 9A is the principal part sectional view of the active elementregion ACTj illustrated in FIG. 8B. In the case of the trench structure,it is preferable to set the depth of the gate electrode p+gate (“depth”in the figure), that is, the channel length of the SiCJFET, to at leasthim or greater. When the gate electrode depth “depth” is large, it ispossible to make high the electrostatic potential in the channel at thetime when the SiCJFET is in an OFF state. Therefore, it is possible toreduce the leakage current between the drain and the source, comparedwith the structure in which the gate electrode has a shallow depth ofabout 0.5 μm. In this case, the drain leakage current flows into thegate electrode p+gate; therefore, after the SiCJFET is cut off, it ispossible to suppress the rise of the source voltage of the SiCJFET, andhence, the drain potential of the Si-type MOSFET in cascade connection.That is, by adopting the element structure described with reference toFIG. 9A in the SiCJFET 3 described in Embodiment 1, it is possible toprovide the more reliable semiconductor device of which the Si-typeMOSFET 4 is hard to be destroyed. It is needless to say that it ispossible to realize a switching circuit SW with a large current densityby employing the SiCJFET of the trench structure. FIG. 9B illustrates across section of a vertical-type SiCJFET which does not have the trenchstructure. That is, FIG. 9B is not a principal part sectional view ofthe active element region ACTj illustrated in FIG. 8B, but illustratesanother embodiment. In this case, there is an advantage that the elementstructure is simple and the production cost is low. In FIG. 9A, the p+layer is formed in a sidewall part by oblique ion implantation or othermeans; on the contrary, in FIG. 9B, it is not necessary to performoblique ion implantation, and the high degree of accuracy is obtained inthe profile of impurity concentration. Therefore, there is an advantagethat it is possible to easily form the SiCJFET with uniformcharacteristics. As is the case with FIG. 9A, it is preferable to setthe depth of the gate electrode p+gate of the SiCJFT illustrated in FIG.9B to 1 μm or greater. By adopting the structure described above, it ispossible to obtain an effect equivalent to the effect obtained in FIG.9A.

FIG. 10 illustrates an element cross section of the semiconductor chip 2in which the Si-type MOSFET 4 is formed. The plane layout of thesemiconductor chip 2 is the same as that of the semiconductor chip 1, asseen from FIGS. 7A, 7B, and 8A. However, the area of the source pad SPmis smaller than the area of the source pad SPj; consequently thesemiconductor chip 2 is smaller than the semiconductor chip 1. Asillustrated in FIG. 10, a drift layer DRIFTm is located over a siliconsemiconductor substrate SUBm. A drain electrode DRAINm is located underthe silicon semiconductor substrate SUBm. A P-type semiconductor area Pexists in the drift layer DRIFTm, and an N-type semiconductor area N+exists in the P-type semiconductor area P. A gate electrode GPm islocated over the N-type semiconductor area N+, the P-type semiconductorarea P, and the drift layer DRIFTm, through the intermediary of an oxidefilm Tox. A source electrode SPm is located over the N-typesemiconductor area N+ and the P-type semiconductor area P. The gateelectrode GPm and the source electrode SPm are separated. As understoodfrom FIG. 10, this Si-type MOSFET is the so-called vertical-type MOSFETof a bottom drain type. By employing the MOSFET with the structureillustrated in FIG. 10 as the Si-type MOSFET 4 described in Embodiment1, it is possible to realize a switching element with a larger currentdensity. That is, it is possible to reduce the on-resistance of theswitching elements coupled in cascade; accordingly, it becomes possibleto provide a switching circuit SW with a reduced loss.

According to the embodiment described above, the semiconductor devicecomprises a pair of terminals, a silicon transistor, and a compoundtransistor, in which the source-to-drain paths of the silicon transistorand the compound transistor are coupled in cascade between the pair ofterminals, and the silicon transistor and the compound transistor aredriven on the basis of one input signal (an input signal which turns onand off the switching circuit) so as to have a period in which bothtransistors are set in an OFF state. By setting both transistors in anOFF state according to the input signal, it becomes possible to enhancethe reduction of a leakage current which flows between the pair ofterminals. When the pair of terminals are set conducted (set in an ONstate), the semiconductor device is driven so as to set the silicontransistor in an ON state before setting the compound transistor in anON state. By this setting, it becomes possible to suppress a surgepotential which is generated by the parasitic impedance of a wiringcoupling the compound transistor and the silicon transistor, andconsequently it becomes possible to reduce a possibility of destructionof the transistors. Furthermore, when the pair of terminals are setnon-conducted (set in an OFF state), the semiconductor device is drivenso as to set the compound transistor in an OFF state before setting thesilicon transistor in an OFF state. By this setting, it becomes possibleto enhance the reduction of the surge potential generated by theparasitic impedance, and consequently it becomes possible to reduce apossibility of destruction of the transistors.

The embodiment described above has presented the example in whichsilicon carbide (SiC) is employed as a material of a JFET. However,compound semiconductors, such as a gallium nitride (GaN), may beemployed as a material. For example, by employing a gallium nitride(GaN) as a material of a JFET of an inverter circuit and by applying theembodiment described above, it is possible to make the inverter circuitperform switching at an increased operating frequency. Consequently, thepassive element employed for the inverter circuit can be miniaturized;therefore, it is possible to enhance the reduction in size and therealization of low cost of the power conversion system. FIG. 3illustrates the application of the three-phase inverter circuit;however, the application is not restricted to the example naturally. Itis needless to say that the same effect is obtained even when thesemiconductor device according to the present invention is applied tovarious systems, for example, an inverter device of an air-conditioner,a power conditioner of a solar energy power generation system, aninverter device for driving of a hybrid car, and others.

As described above, the invention accomplished by the present inventorshas been concretely described based on the embodiments. However, itcannot be overemphasized that the present invention is not restricted tothe embodiments, and it can be changed variously in the range which doesnot deviate from the gist.

What is claimed is:
 1. A semiconductor device comprising: a pair ofterminals; a normally-off first transistor provided with a gate, asource, and a drain; and a normally-on second transistor which is a SiCcompound transistor provided with a gate, a source, and a drain, ofwhich a source-to-drain path is coupled between the pair of terminalsvia a source-to-drain path of the first transistor, wherein the gate ofthe first transistor and the gate of the second transistor are bothdriven to have a period in which the second transistor is set to an offstate before the first transistor.
 2. The semiconductor device accordingto claim 1, wherein the first transistor is a MOSFET.
 3. Thesemiconductor device according to claim 1, wherein, the gate of thefirst transistor and the gate of the second transistor are both drivento have another period in which the first transistor is set to an onstate before the second transistor.
 4. The semiconductor deviceaccording to claim 3, wherein the second transistor and the firsttransistor are sealed in one package, wherein the gate of the firsttransistor is coupled to a first lead projected from the package,wherein the source of the first transistor is coupled to a second leadprojected from the package, wherein the gate of the second transistor iscoupled to a third lead projected from the package, and wherein thedrain of the second transistor is coupled to a fourth lead projectedfrom the package.
 5. The semiconductor device according to claim 1,further comprising: a delay circuit which receives one input signal todrive both the first transistor and the second transistor, and has aplurality of first inverters to delay the one input signal to drive thefirst transistor when setting the first transistor and the secondtransistor to the off state.
 6. The semiconductor device according toclaim 1, wherein the delay circuit further has a plurality of secondinverters to delay the one input signal to drive the second transistorwhen setting the first transistor and the second transistor to an onstate.
 7. A system comprising: a load device; and a first semiconductordevice and a second semiconductor device each coupled to the loaddevice, wherein each of the first semiconductor device and the secondsemiconductor device comprise: a pair of terminals, a normally-off firsttransistor provided with a gate, a source, and a drain, a normally-onsecond transistor which is a SiC compound transistor provided with agate, a source, and a drain, of which a source-to-drain path is coupledbetween the pair of terminals via a source-to-drain path of the firsttransistor, wherein the gate of the first transistor and the gate of thesecond transistor are both driven to have a period in which the secondtransistor is set to an off state before the first transistor, andwherein one of the pair of terminals in the first semiconductor deviceis coupled to the load device, and one of the pair of terminals in thesecond semiconductor device is coupled to the load device.
 8. The systemaccording to claim 7, wherein each of the first semiconductor device andthe second semiconductor device further comprise: a delay circuit whichreceives one input signal to drive both the first transistor and thesecond transistor, and has a plurality of first inverters to delay theone input signal to the first transistor when setting the firsttransistor and the second transistor to the off state.
 9. The systemaccording to claim 8, wherein the delay circuit further has a pluralityof second inverters to delay the one input signal to the secondtransistor when setting the first transistor and the second transistorto an on state.
 10. The system according to claim 9, wherein the firsttransistor is set to the on state before the second transistor.
 11. Thesystem according to claim 7, wherein in each of the first semiconductordevice and the second semiconductor device, the first transistor is aMOSFET.
 12. The system according to claim 7, wherein, when one of thefirst transistor and the second transistor in the first semiconductordevice is set to an on state, the first transistor and the secondtransistor in the second semiconductor device are set to the off state.13. The system according to claim 12, wherein the load device includes amotor.
 14. The system according to claim 12, wherein the load deviceincludes a coil.
 15. A system comprising: a load device; an invertercircuit coupled to the load device, and which comprises: a pair ofterminals, a normally-off first transistor provided with a gate, asource, and a drain, and a normally-on second transistor which is a SiCcompound transistor provided with a gate, a source, and a drain, ofwhich a source-to-drain path is coupled between the pair of terminalsvia a source-to-drain path of the first transistor; a control circuit todrive the inverter circuit, and, in response to an input signal, thecontrol circuit supplies a first control signal to the gate of the firsttransistor and a second control signal to the gate of the secondtransistor, so the first transistor and the second transistor have aperiod in which the second transistor is set to an off state before thefirst transistor; and a delay circuit which receives the one inputsignal, and has a plurality of first inverters to delay the firstcontrol signal to the first transistor when setting the first transistorand the second transistor to the off state.
 16. The semiconductor deviceaccording to claim 15, wherein the delay circuit has a plurality ofsecond inverters to delay the second control signal to the secondtransistor when setting the first transistor and the second transistorto an on state.
 17. The semiconductor device according to claim 15,wherein the first transistor is a MOSFET.
 18. The semiconductor deviceaccording to claim 15, wherein, when setting the first transistor andthe second transistor to an on state, the first transistor is set to theon state before the second transistor.
 19. The semiconductor deviceaccording to claim 18, wherein, when the first transistor and the secondtransistor are set to the on state, the pair of terminals are set to aconductive state.
 20. The semiconductor device according to claim 15,wherein, when the first transistor and the second transistor are set tothe off state, the pair of terminals are set to a non-conductive state.